Cirrus Logic CS4234 - Manual (Page 42)

DS899F1 42
CS4234
4.6.5.2 Generating the Tracking Signal Inside an External DSP
If the tracking signal is to be generated within an external DSP, the tracking signal generation blocks men-
tioned above can be bypassed by setting the
“DAC5 CFG & FLTR[1:0]” bits in the "DAC Control
1" register to either the interpolation filter option (‘00’) or the sample and hold filter (’01’). Note that the
DAC5 signal inversion caused by setting the “TPS MODE” bit in the "TPS Control" register is not by-
passed and for most cases the bit should be cleared, see Figure 29 . The “DAC5 SOURCE[2:0]” bits in the
"SP Control" register advise the CS4234 where the tracking signal can be found among the incoming da-
ta. If the tracking signal has been coded into one of the 32 slots of the TDM stream, the signal can be
routed into the DAC5 path by masking all of the other slots via the SDINx Maskx bits. As shown in the
“DAC5 SOURCE[2:0]” bits in the "SP Control" register , the tracking signal can also be coded into the
LSBs of the 16 slots of the SDIN1 stream.
4.6.5.3 Using DAC5 in a Traditional DAC Configuration (with no tracking signal)
As mentioned previously, DAC5 is identical in performance to the DACs in the DAC1-4 path. In this appli-
cation, signal is routed into the DAC5 path in the same manner as in the previous section. If the data for
DAC5 is in one of the 32 slots, simply unmask the appropriate slot by using the appropriate mask bits. If
the data is coded into the LSBs of SDIN1, set the
“DAC5 SOURCE[2:0]” bits in the "SP Control" register
appropriately.
Please refer to Section 4.6.6 Volume Control regarding volume control within the DAC5 path. The opera-
tion is identical to the volume control in the DAC1-4 path.
One additional control that is present within the DAC5 path is the “DAC5 MVC” bit in the "DAC Control
1" register . When this bit is set, the CS4234 will apply any gain written to the master volume control reg-
ister to the DAC5 path as well. If this bit is cleared, the DAC5 volume will operate independently of the
setting of the master volume control register. This feature is provided to ensure that, when not desired,
any changes made to the master volume control on the audio path will not affect the output amplitude of
the tracking power supply signal, when DAC5 is used for that application.
4.6.5.4 De-emphasis Filter
The CS4234 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz sample rates. It is not support-
ed for 96 kHz or for any settings in Double Speed Mode. The filter response is adjusted to be appropriate
for a particular sample rate by the
Base Rate Advisory bits. This filter response, shown in Figure 25 , will
vary if these bits are not set appropriately for the given sample rate. The frequency response of the de-
emphasis curve scales proportionally with changes in sample rate, F
S
. Please see Section 6.15.3 DAC5
De-emphasis for de-emphasis control.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s preemphasis
equalization as a means of noise reduction.
4.6.5.5 Filter Options
There are two internal filter options for the DAC5 path. A standard interpolation filter is provided for tradi-
tional applications as well as a “sample and hold” bypass option. To activate the bypass, set the
“DAC5
CFG & FLTR[1:0]” bits in the "DAC Control 1" register to ‘01’.
4.6.6 Volume Control
The CS4234 includes a volume control for the DAC1-4 and DAC5 signal paths. While the general opera-
tion of the volume controls is identical between the two paths, the optional tracking power supply control
present in the DAC5 path modifies the implementation slightly. The implementation details for the volume