Cirrus Logic CS4234 User Manual
Page 3
DS899F1
3
CS4234
TABLE OF CONTENTS
2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 8
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 9
RECOMMENDED OPERATING CONDITIONS .................................................................................... 9
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 9
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 10
TYPICAL CURRENT CONSUMPTION ............................................................................................... 11
ANALOG INPUT CHARACTERISTICS .............................................................................................. 12
ADC DIGITAL FILTER CHARACTERISTICS ...................................................................................... 14
ANALOG OUTPUT CHARACTERISTICS ........................................................................................... 15
COMBINED DAC INTERPOLATION AND ON-CHIP ANALOG FILTER RESPONSE ........................ 16
DIGITAL I/O CHARACTERISTICS ...................................................................................................... 17
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE .................................................... 18
SWITCHING SPECIFICATIONS - CONTROL PORT .......................................................................... 20
4.1 Power Supply Decoupling, Grounding, and PCB Layout ............................................................... 21
4.2 Recommended Power-Up and Power-Down Sequence ................................................................ 21
4.3 I²C Control Port .............................................................................................................................. 25
4.4 System Clocking ............................................................................................................................ 26
4.5 Serial Port Interface ....................................................................................................................... 28
4.6 Internal Signal Path ....................................................................................................................... 32
4.7 Reset Line ...................................................................................................................................... 47
4.8 Error Reporting and Interrupt Behavior .......................................................................................... 47
5. REGISTER QUICK REFERENCE ........................................................................................................ 50
6. REGISTER DESCRIPTIONS ................................................................................................................ 52
6.1 Device I.D. A and B (Address 01h) (Read Only)
Device I.D. C and D (Address 02h) (Read Only)
Device I.D. E and F (Address 03h) (Read Only) ............................................................................... 52
6.2 Revision I.D. (Address 05h) (Read Only) ....................................................................................... 52
6.3 Clock and SP Select (Address 06h) ............................................................................................... 53
6.4 Sample Width Select (Address 07h) .............................................................................................. 54
6.5 Serial Port Control (Address 08h) .................................................................................................. 55
6.6 Serial Port Data Select (Address 09h) ........................................................................................... 56
6.7 Serial Data Input 1 Mask 1 (Address 0Ah) ..................................................................................... 57
6.8 Serial Data Input 1 Mask 2 (Address 0Bh) ..................................................................................... 57
6.9 Serial Data Input 2 Mask 1 (Address 0Ch) .................................................................................... 58
6.10 Serial Data Input 2 Mask 2 (Address 0Dh) .................................................................................. 58
6.11 Tracking Power Supply Control (Address 0Eh) ........................................................................... 59
6.12 ADC Control 1 (Address 0Fh) ...................................................................................................... 60
6.13 ADC Control 2 (Address 10h) ...................................................................................................... 61
6.14 Low Latency Path Control (Address 11h) .................................................................................... 61
6.15 DAC Control 1 (Address 12h) ...................................................................................................... 62
6.16 DAC Control 2 (Address 13h) ...................................................................................................... 63
6.17 DAC Control 3 (Address 14h) ...................................................................................................... 63
6.18 DAC Control 4 (Address 15h) ...................................................................................................... 64
6.19 Volume Mode (Address 16h) ....................................................................................................... 65
6.20 Master and DAC1-5 Volume Control (Address 17h, 18h, 19h, 1Ah, 1Bh, and 1Ch) ................... 66
6.21 Interrupt Control (Address 1Eh) ................................................................................................... 66
6.22 Interrupt Mask 1 (Address 1Fh) ................................................................................................... 67
6.23 Interrupt Mask 2 (Address 20h) ................................................................................................... 68
6.24 Interrupt Notification 1 (Address 21h) (Read Only) ...................................................................... 68