Sdram refresh cycle, Figure 6. sdram refresh cycle timing measurement, Figure 6 – Cirrus Logic EP7312 User Manual
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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
SDRAM Refresh Cycle
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
SDCLK
SDCS
SDRAS
SDCAS
SDQM
[3:0]
SDMWE
SDATA
ADDR
t
CSa
t
RAa
t
CSd
t
RAd
t
CAa
t
CAd
Figure 6. SDRAM Refresh Cycle Timing Measurement
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