Cirrus Logic EP7312 - Manual (Page 43)

DS508F2
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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 43
EP7312
High-Performance, Low-Power System on Chip
J7 CTS I UART 1 clear to send input
J8 VSSRTC RTC ground Real time clock ground
J9 VSSRTC RTC ground Real time clock ground
J10 A[17]/DRA[10] 1 Low O System byte address / SDRAM address
J11 A[16]/DRA[11] 1 Low O System byte address / SDRAM address
J12 A[15]/DRA[12] 1 Low O System byte address / SDRAM address
J13 A[14]/DRA[13] 1 Low O System byte address / SDRAM address
J14 nTRST I JTAG async reset input
J15 D[16] 1 Low I/O Data I/O
J16 D[17] 1 Low I/O Data I/O
K1 LEDDRV 1 Low O IR LED drive
K2 PHDIN I Photodiode input
K3 VSSIO Pad ground I/O ground
K4 DCD I UART 1 data carrier detect
K5 nTEST[1] With p/u* I Test mode select input
K6 EINT[3] I External interrupt
K7 VSSRTC RTC ground Real time clock ground
K8 ADCIN I SSI1 ADC serial input
K9 COL[4] 1 High O Keyboard scanner column drive
K10 TCLK I JTAG clock
K11 D[20] 1 Low I/O Data I/O
K12 D[19] 1 Low I/O Data I/O
K13 D[18] 1 Low I/O Data I/O
K14 VSSIO Pad ground I/O ground
K15 VDDIO Pad power Digital I/O power, 3.3V
K16 VDDIO Pad power Digital I/O power, 3.3V
L1 RXD[1] I UART 1 receive data input
L2 DSR I UART 1 data set ready input
L3 VDDIO Pad power Digital I/O power, 3.3V
L4 nEINT[1] I External interrupt input
L5 PE[2]/CLKSEL 1
Input
‡
I/O GPIO port E / clock input mode select
L6 VSSRTC RTC ground Real time clock ground
L7 PD[0]/LEDFLSH 1 Low I/O GPIO port D / LED blinker output
L8 VSSRTC Core ground Real time clock ground
L9 COL[6] 1 High O Keyboard scanner column drive
L10 D[31] 1 Low I/O Data I/O
L11 VSSRTC RTC ground Real time clock ground
L12 A[22]/DRA[5] 1 Low O System byte address / SDRAM address
L13 A[21]/DRA[6] 1 Low O System byte address / SDRAM address
L14 VSSIO Pad ground I/O ground
L15 A[18]/DRA[9] 1 Low O System byte address / SDRAM address
L16 A[19]/DRA[8] 1 Low O System byte address / SDRAM address
M1 nTEST[0] With p/u* I Test mode select input
M2 nEINT[2] I External interrupt input
M3 VDDIO Pad power Digital I/O power, 3.3V
M4 PE[0]/BOOTSEL[0] 1
Input
‡
I GPIO port E / Boot mode select
M5 TMS with p/u* I JTAG mode select
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location Name
Strength
† Reset
State
Type Description