Cirrus Logic EP7312 User Manual
Page 46
46
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
9
F4
TXD2
O
14
10
E1
RXD2
I
16
13
E2
PB[7]
I/O
17
14
G5
PB[6]
I/O
20
15
F1
PB[5]
I/O
23
16
G4
PB[4]
I/O
26
17
F2
PB[3]
I/O
29
18
H7
PB[2]
I/O
32
19
G1
PB[1]
I/O
35
20
H6
PB[0]
I/O
38
23
H1
PA[7]
I/O
41
24
H5
PA[6]
I/O
44
25
H2
PA[5]
I/O
47
26
H4
PA[4]
I/O
50
27
J1
PA[3]
I/O
53
28
J4
PA[2]
I/O
56
29
J2
PA[1]
I/O
59
30
J5
PA[0]
I/O
62
31
K1
LEDDRV
O
65
32
J6
TXD1
O
67
34
K2
PHDIN
I
69
35
J7
CTS
I
70
36
L1
RXD1
I
71
37
K4
DCD
I
72
38
L2
DSR
I
73
39
K5
nTEST1
I
74
40
M1
nTEST0
I
75
41
K6
EINT3
I
76
42
M2
nEINT2
I
77
43
L4
nEINT1
I
78
44
N1
nEXTFIQ
I
79
45
L5
PE[2]/CLKSEL
I/O
80
46
N2
PE[1]/
BOOTSEL[1]
I/O
83
47
M4
PE[0]/BOOTSEL0
I/O
86
53
T2
PD[7]/SDQM[1]
I/O
89
54
T3
PD[6/SDQM[0]]
I/O
92
55
N5
PD[5]
I/O
95
56
R3
PD[4]
I/O
98
59
T4
PD[3]
I/O
101
60
N6
PD[2]
I/O
104
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position