Cirrus Logic EP7312 User Manual
Page 47
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
47
EP7312
High-Performance, Low-Power System on Chip
61
R4
PD[1]
I/O
107
62
L7
PD[0]/LEDFLSH
O
110
68
T6
SSIRXFR
I/O
122
69
K8
ADCIN
I
125
70
R6
nADCCS
O
126
75
M8
DRIVE1
I/O
128
76
T8
DRIVE0
I/O
131
77
N8
ADCCLK
O
134
78
R8
ADCOUT
O
136
79
N9
SMPCLK
O
138
80
T9
FB1
I
140
82
M9
FB0
I
141
83
R9
COL7
O
142
84
L9
COL6
O
144
85
T10
COL5
O
146
86
K9
COL4
O
148
87
R10
COL3
O
150
88
N10
COL2
O
152
91
R11
COL1
O
154
92
M10
COL0
O
156
93
T12
BUZ
O
158
94
L10
D[31]
I/O
160
95
R12
D[30]
I/O
163
96
N11
D[29]
I/O
166
97
T13
D[28]
I/O
169
99
R13
A[27]/DRA[0]
Out
172
100
M11
D[27]
I/O
174
101
T14
A[26]/DRA[1]
O
177
102
N12
D[26]
I/O
179
103
R14
A[25]/DRA[2]
O
182
104
T15
D[25]
I/O
184
105
N13
HALFWORD
O
187
106
R16
A[24]/DRA[3]
O
189
109
P15
D[24]
I/O
191
110
M13
A[23]/DRA[4]
O
194
111
N16
D[23]
I/O
196
112
L12
A[22]/DRA[5]
O
199
113
N15
D[22]
I/O
201
114
L13
A[21]/DRA[6]
O
204
115
M16
D[21]
I/O
206
117
M15
A[20]/DRA[7]
O
209
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position