Cirrus Logic EP7312 - Manual (Page 45)

DS508F2

Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 45
EP7312
High-Performance, Low-Power System on Chip
*
“With p/u” means with internal pull-up of 100 KOhms on the pin.
† Strength 1 = 4 ma
Strength 2 = 12 ma
‡
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
JTAG Boundary Scan Signal Ordering
R5 SSITXDA 1 Low O DAI/CODEC/SSI2 serial data output
R6 nADCCS 1 High O SSI1 ADC chip select
R7 VDDIO Pad power Digital I/O power, 3.3V
R8 ADCOUT 1 Low O SSI1 ADC serial data output
R9 COL[7] 1 High O Keyboard scanner column drive
R10 COL[3] 1 High O Keyboard scanner column drive
R11 COL[1] 1 High O Keyboard scanner column drive
R12 D[30] 1 Low I/O Data I/O
R13 A[27]/DRA[0] 2 Low O System byte address / SDRAM address
R14 A[25]/DRA[2] 2 Low O System byte address / SDRAM address
R15 VDDIO Pad power Digital I/O power, 3.3V
R16 A[24]/DRA[3] 1 Low O System byte address / SDRAM address
T1 VDDRTC RTC power Real time clock power, 2.5V
T2 PD[7]/SDQM[1] 1 Low I/O GPIO port D / SDRAM byte lane mask
T3 PD[6]/SDQM[0] 1 Low I/O GPIO port D / SDRAM byte lane mask
T4 PD[3] 1 Low I/O GPIO port D
T5 SSICLK 1
Input
‡
I/O DAI/CODEC/SSI2 serial clock
T6 SSIRXFR 1
Input
‡ I/O DAI/CODEC/SSI2 frame sync
T7 VDDCORE Core power Core power, 2.5V
T8 DRIVE[0] 2
High /
Low
I/O PWM drive output
T9 FB[1] I PWM feedback input
T10 COL[5] 1 High O Keyboard scanner column drive
T11 VDDIO Pad power Digital I/O power, 3.3V
T12 BUZ 1 Low O Buzzer drive output
T13 D[28] 1 Low I/O Data I/O
T14 A[26]/DRA[1] 2 Low O System byte address / SDRAM address
T15 D[25] 1 Low I/O Data I/O
T16 VSSIO Pad ground I/O ground
Table 22. JTAG Boundary Scan Signal Ordering
LQFP
Pin No.
PBGA
Ball
Signal Type Position
1 B1 nCS[5] O 1
4 C2 EXPCLK I/O 3
5 E4 WORD O 6
6 D1 WRITE/nSDRAS O 8
7 F5 RUN/CLKEN O 10
8 D2 EXPRDY I 13
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location Name
Strength
† Reset
State
Type Description