Cirrus Logic EP7312 User Manual
Page 49
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
49
EP7312
High-Performance, Low-Power System on Chip
1) See
EP7312 Users’ Manual
for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input, output, then enable as applicable.
171
A11
A[3]
O
302
172
G9
D[3]
I/O
304
173
B11
A[2]
O
307
175
A10
D[2]
I/O
309
176
F9
A[1]
O
312
177
B10
D[1]
I/O
314
178
E9
A[0]
O
317
179
A9
D[0]
I/O
319
184
D8
CL2
O
322
185
B8
CL1
O
324
186
E8
FRM
O
326
187
A7
M
O
328
188
F8
DD[3]
O
330
189
B7
DD[2]
O
333
191
A6
DD[1]
O
336
192
G8
DD[0]
O
339
193
B6
nSDCS[1]
O
342
194
D7
nSDCS[0]
O
344
195
A5
SDQM[3]
I/O
346
196
E7
SDQM[2]
I/O
349
199
F7
SDCKE
I/O
352
200
A4
SDCLK
I/O
355
201
D6
nMWE/nSDWE
O
358
202
B4
nMOE/nSDCAS
O
360
204
E6
nCS[0]
O
362
205
A3
nCS[1]
O
364
206
D5
nCS[2]
O
366
207
B3
nCS[3]
O
368
208
A2
nCS[4]
O
370
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position