Cirrus Logic EP7312 - Manual (Page 29)

DS508F2

Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 29
EP7312
High-Performance, Low-Power System on Chip
JTAG Interface
Parameter Symbol Min Max Units
TCK clock period t
clk_per
2 - ns
TCK clock high time t
clk_high 1 - ns
TCK clock low time t
clk_low
1 - ns
JTAG port setup time t
JPs
- 0 ns
JTAG port hold time t
JPh
- 3 ns
JTAG port clock to output t
JPco
- 10 ns
JTAG port high impedance to valid output t
JPzx
- 12 ns
JTAG port valid output to high impedance t
JPxz
- 19 ns
TDO
TCK
TDI
TMS
t
JPh
t
clk_high
t
clk_low
t
JPzx
t
JPco
t
JPxz
t
clk_per
t
JPs
Figure 14. JTAG Timing Measurement