Cirrus Logic EP7312 - Manual (Page 40)

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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS508F2
EP7312
High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table 21. 256-Ball PBGA Ball Listing
Ball Location Name
Strength
† Reset
State
Type Description
A1 VDDIO Pad power Digital I/O power, 3.3 V
A2 nCS[4] 1 High O Chip select 4
A3 nCS[1] 1 High O Chip select 1
A4 SDCLK 2 Low O SDRAM clock out
A5 SDQM[3] 2 Low O SDRAM byte lane mask
A6 DD[1] 1 Low O LCD serial display data
A7 M 1 Low O LCD AC bias drive
A8 VDDIO Pad power Digital I/O power, 3.3 V
A9 D[0] 1 Low I/O Data I/O
A10 D[2] 1 Low I/O Data I/O
A11 A[3] 2 Low O System byte address
A12 VDDIO Pad power Digital I/O power, 3.3V
A13 A[6] 1 Low O System byte address
A14 MOSCOUT O Main oscillator out
A15 VDDOSC Oscillator power Oscillator power in, 2.5 V
A16 VSSIO Pad ground I/O ground
B1 nCS[5] 1 Low O Chip select 5
B2 VDDIO Pad power Digital I/O power, 3.3 V
B3 nCS[3] 1 High O Chip select 3
B4 nMOE/nSDCAS 1 High O ROM, expansion OP enable/SDRAM CAS control signal
B5 VDDIO Pad power Digital I/O power, 3.3 V
B6 nSDCS[1] 1 High O SDRAM chip select 1
B7 DD[2] 1 Low O LCD serial display data
B8 CL[1] 1 Low O LCD line clock
B9 VDDCORE Core power Digital core power, 2.5V
B10 D[1] 1 Low I/O Data I/O
B11 A[2] 2 Low O System byte address
B12 A[4] 1 Low O System byte address
B13 A[5] 1 Low O System byte address
B14 WAKEUP Schmitt I System wake up input
B15 VDDIO Pad power Digital I/O power, 3.3 V
B16 nURESET Schmitt I User reset input
C1 VDDIO Pad power Digital I/O power, 3.3V
C2 EXPCLK 1 I Expansion clock input
C3 VSSIO Pad ground I/O ground
C4 VDDIO Pad power Digital I/O power, 3.3 V
C5 VSSIO Pad ground I/O ground
C6 VSSIO Pad ground I/O ground
C7 VSSIO Pad ground I/O ground
C8 VDDIO Pad power Digital I/O power, 3.3 V
C9 VSSIO Pad ground I/O ground
C10 VSSIO Pad ground I/O ground
C11 VSSIO Pad ground I/O ground
C12 VDDIO Pad power Digital I/O power, 3.3 V
C13 VSSIO Pad ground I/O ground