ADLINK PXI-2502 - Manual (Page 45)

Operation Theorem
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4.4 General Purpose Timer/Counter Operation
Two independent 16-bit up/down timer/counter are embedded in FPGA
firmware for users applications. They have the following features:
•
Direction of counting can be controlled via hardware or software.
•
Selectable c ounter clock source from either internal or external clock up
to 10MHz.
•
Programmable gate selection.
•
Programmable input and output signal polarities, either active-high or
active-low.
•
Initial Count can be loaded via software
•
Current count value can be read-back by software without affecting
circuit operation
4.4.1 Timer/Counter functions basics
Each timer/counter has three inputs that can be controlled via hardware or
software. They are clock input (GPTC_CLK), gate input (GPTC_GATE),
and up/down control input (GPTC_UPDOWN).
The GPTC_CLK input acts as a clock source to the timer/counter. Active
edges on the GPTC_CLK input increment or decrement the counter. The
GPTC_UPDOWN input determines whether the counter’s counting-up or
counting-down. The GPTC_GATE input is a control line, which acts as a
counter enable or a counter trigger signal in different modes.
The output of timer/counter is GPTC_OUT. After power-up, GPTC_OUT is
pulled high by a 10K resistor. GPTC_OUT goes low after the DAQ board is
initialized.
All the polarities of input/output signals can be programmed via software.
In this chapter, all timing figures assume that GPTC_CLK, GPTC_GATE,
and GPTC_OUT are set to be positive-logic. (i.e. they’re triggered on the
rising-edge)
4.4.2 General Purpose Timer/Counter modes
Eight programmable timer/counter modes are provided. All modes start
operations following the software start command. The GPTC software
reset command initializes the status of the counter and re-loads the initial
value to the counter.