Altera Parallel Flash Loader IP - Manual (Page 19)

For the FPP configuration scheme, the enhanced bitstream compression feature helps achieve higher
configuration data compression ratio and faster configuration time. For the PS configuration scheme, the
double compression technique helps achieve higher configuration data compression ratio and moderate
configuration time. To enable the double compression technique, turn on both the typical bitstream
compression feature and the enhanced bitstream compression feature in the PFL parameter editor.
Figure 15: FPGA Configuration Data Flow with Enhanced Bitstream Compression Feature in PS or FPP
Configuration Scheme
Altera CPLD
CFI or Quad SPI
Flash Memory
Altera
FPGA
PFL with
Enhanced
Bitstream
Decompression
Feature
Compressed Data
Passive Serial or
Fast Passive Parallel With
Uncompressed Data
Figure 16: FPGA Configuration Data Flow with Double Compression Technique in PS Configuration
Scheme
Altera CPLD
CFI or Quad SPI
Flash Memory
PFL with
Enhanced
Bitstream
Decompression
Feature
Double Compressed
Data
Passive Serial With
Compressed Data
Altera FPGA
On-Chip
Bitstream
Decompression
Feature
Note: The enhanced bitstream compression and decompression feature is available in the PFL IP core in
the Quartus II software version 10.0 onwards.
UG-01082
2015.01.23
Using Enhanced Bitstream Compression and Decompression 19
Parallel Flash Loader IP Core User Guide Altera Corporation
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