Altera Parallel Flash Loader IP User Manual
Page 53
Example 3: Page Mode
• Page mode configuration time calculation:
.rbf size for EP2S15 = 577 KB = 590,848 Bytes
Configuration mode = FPP without data compression or encryption
Flash access mode = Page Mode
Flash data bus width = 16 bits
Flash access time = 100 ns
PFL input Clock = 100 MHz
DCLK ratio = 2
• Use the following formulas in this calculation:
Tpage_access = 30 ns
Caccess = [(Taccess*Fclk+1) + (Tpage_access*Fclk*15)]/16
Cflash for Page Mode = Caccess / 2
Ccfg = 2.5
Coverhead = 3* Caccess
Total Clock Cycles = Coverhead + max (Cflash, Ccfg)*N
Total Configuration Time = Total Clock Cycle/ PFL Input Clock
• Substitute these values in the following formulas:
Caccess = [((100ns * 100 MHz) + 1) + (30ns*100 MHz*15)]/16 = 3.5
Cflash for Page Mode = 3.5/ 2 = 1.75 = 2
Ccfg = 2.5
Coverhead = 3*3.5 = 10.5
Total Clock Cycles = 10.5 + 2.5*590848 = 1477130.5
Total Configuration Time at 100 MHz = 1477130.5 / 100 × 106 = 14.77 ms
UG-01082
2015.01.23
Specifications
53
Parallel Flash Loader IP Core User Guide
Altera Corporation