Altera Parallel Flash Loader IP - Manual (Page 7)

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Supported Schemes and Features
The PFL IP core allows you to configure the FPGA in passive serial (PS) or fast passive parallel (FPP)
scheme. The PFL IP core supports configuration with FPGA on-chip data compression and data
encryption.
When you use compressed or encrypted configuration data for FPP configuration, the PFL IP core holds
one data byte for one, two, four, or eight DCLK cycles to ensure the DCLK frequency runs at the required
data rate as specified by the DCLK-to-DATA[] Ratio. The PFL IP core checks if the compression or
encryption feature is turned on in the configuration image before configuring in FPP mode. Hence, no
additional setting is required in the PFL IP core to specify whether the configuration file stored in the
flash memory device is a compressed or uncompressed image.
Note: When you turn on the enhanced bitstream compression feature, data encryption is disabled.
You can program the Altera CPLDs and flash memory device in Programmer Object File (
.pof
), Jam
™
Standard Test and Programming Language (STAPL) Format File ( .jam ), or JAM Byte Code File ( .jbc ) file
format. The PFL IP core does not support Raw Binary File ( .rbf ) format.
Logic element (LE) usage varies with different PFL IP core and Quartus II software settings. To determine
the exact LE usage number, compile a PFL design with your settings using the Quartus II software.
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard
™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
The IP Catalog lists IP cores available for your design. Double-click any IP core to launch the parameter
editor and generate files representing your IP variation. The parameter editor prompts you to specify an
IP variation name, optional ports, and output file generation options. The parameter editor generates a
top-level Qsys system file ( .qsys ) or Quartus II IP file ( .qip ) representing the IP core in your project. You
can also parameterize an IP variation without an open project.
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families.
• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access
partner IP information on the Altera website.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, andor view links to documentation.
UG-01082
2015.01.23
Supported Schemes and Features 7
Parallel Flash Loader IP Core User Guide Altera Corporation
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