Altera PowerPlay Early Power Estimator - Manual (Page 25)

Altera Corporation 3–9
October 2005 PowerPlay Early Power Estimator User Guide: Stratix, Stratix GX & Cyclone FPGAs
Using PowerPlay Early Power Estimator for Stratix, Stratix GX & Cyclone FPGAs
Each row in the Digital Signal Processing (DSP) Blocks section
represents a DSP design module where the DSP block(s) have the same
frequency, number of data outputs, and toggle percentage. If some (or all)
DSP blocks in your design have different configurations, you need to
enter the information in different rows. For each DSP module, you need
to enter the clock frequency (f
MAX
) in MHz, the number of data outputs
per DSP block, the toggle percentage of the data outputs, and the number
of DSP blocks with this configuration.
Table 3–3 describes the values that
are entered in the Digital Signal Processing (DSP) Blocks section of the
PowerPlay early power estimator.
Figure 3–9 shows the Stratix device PowerPlay early power estimator and
the estimated power consumed by the DSP blocks for a design targeting
a Stratix device that uses two DSP blocks clocked by a 250-MHz clock in
36 × 36 mode with a 12.5% toggle rate for the data outputs.
Figure 3–9. Digital Signal Processing Blocks Section in the Stratix PowerPlay Early Power Estimator
Table 3–3. Digital Signal Processing (DSP) Blocks Section Information
Column Heading Description
DSP Module In this column, you can enter a name for the DSP module. This is an optional value.
f
M A X
(MHz) The frequency of the clock feeding the DSP blocks. The maximum clock frequency for DSP
blocks is 340 MHz.
# Data Outputs The number of outputs per DSP block. The number of outputs per DSP block are found in the
Quartus II software timing closure floorplan. This number must be an integer value from 0 to
144.
Toggle % The average percentage of DSP data outputs toggling on each clock cycle. The toggle
percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%. To be more
conservative, you can use a higher toggle percentage.
# DSP blocks The number of DSP blocks that are configured with the same clock frequency, data outputs,
and toggle percentage. This value is limited by the number of DSP blocks available in the
largest device in the family. You need to verify that the number of DSP blocks entered does
not exceed the number of DSP blocks available in your target device because the PowerPlay
early power estimator does not verify this.