Altera PowerPlay Early Power Estimator - Manual (Page 30)

3–14 UG-FPGAPWRCAL-2.0 Altera Corporation
PowerPlay Early Power Estimator User Guide: Stratix, Stratix GX & Cyclone FPGAs October 2005
PowerPlay Early Power Estimator Input Values
domain, the toggle percentage of the serializer outputs, and the I/O
standard used on the output pins.
Table 3–6 describes the values that are
entered in the HSDI section of the PowerPlay early power estimator.
Figure 3–13 shows the Stratix PowerPlay early power estimator and the
estimated power consumed by the HSDI for a design targeting a Stratix
device that has 20 LVDS receiver and transmitter channels operating at
840 Mbps with data outputs toggling at 25%.
1
The power of the receiver and transmitter PLLs used by the
SERDES is included in the HSDI section. Therefore, you do not
need to estimate the receiver and transmitter PLL power in the
PLL section.
Table 3–6. HSDI Section Information
Column Heading Description
Domain Enter a name for the receiver or transmitter domain in this column. This is an optional value.
Data Rate (Mbps) Enter the maximum data rate in Mbps of the receiver or transmitter channels for each
receiver and transmitter domain. Stratix device SERDES circuitry can transmit and receive
data up to 840 Mbps per channel. Therefore, the data rate must be a decimal number from
0 to 840 Mbps.
# of Channels Enter the number of receiver and transmitter channels running at the above data rate.
Since each fast PLL in Stratix devices can support up to 20 high-speed differential
channels, this number must be an integer value from 0 to 20.
VCCIO Select the V
CCIO
used by the receiver channels from the list. The V
CCIO
available for the
receiver channels are 2.5 V and 3.3 V.
Toggle % Enter the average percentage of serializer outputs toggling at each high-speed clock cycle.
The toggle % ranges from 0 to 100%. Typically, the toggle % is 25%. To be more
conservative, you can use a higher toggle percentage.
I/O Standard Select the differential I/O standards used by the transmitter channels from the list. The
differential I/O standards available for the transmitter channels are HyperTransport
technology, LVDS, LVPECL, and 3.3-V PCML.