Altera PowerPlay Early Power Estimator - Manual (Page 3)

Altera Corporation iii
October 2005 PowerPlay Early Power Estimator User Guide: Stratix, Stratix GX & Cyclone FPGAs
Contents
About this User Guide ............................................................................. v
Revision History ........................................................................................................................................ v
How to Contact Altera .............................................................................................................................. v
Typographic Conventions ...................................................................................................................... vi
Chapter 1. About the PowerPlay Early Power Estimator for Stratix, Stratix GX & Cyclone
FPGAs
Release Information ............................................................................................................................... 1–1
Device Family Support ......................................................................................................................... 1–1
General Description ............................................................................................................................... 1–1
Features ................................................................................................................................................... 1–2
Chapter 2. Setting Up PowerPlay Early Power Estimator for Stratix, Stratix GX & Cyclone
FPGAs
System Requirements ............................................................................................................................ 2–1
Download & Install the PowerPlay Early Power Estimator ........................................................... 2–1
Entering Information into the PowerPlay Early Power Estimator ................................................. 2–1
Clearing All Values .......................................................................................................................... 2–1
Entering Global Toggle Rate ........................................................................................................... 2–2
Manually Entering Information ..................................................................................................... 2–2
Importing a File ................................................................................................................................ 2–2
Estimating Power ................................................................................................................................... 2–4
Estimating Power Before Starting the FPGA Design .................................................................. 2–5
Estimating Power While Creating the FPGA Design ................................................................. 2–6
Estimating Power After Completing the FPGA Design ............................................................. 2–7
Chapter 3. Using PowerPlay Early Power Estimator for Stratix, Stratix GX & Cyclone
FPGAs
PowerPlay Early Power Estimator Input Values .............................................................................. 3–1
Device ................................................................................................................................................. 3–1
I
CC
Standby ........................................................................................................................................ 3–2
Clock Network Information ........................................................................................................... 3–2
Logic Elements .................................................................................................................................. 3–5
Digital Signal Processing Blocks .................................................................................................... 3–8
Phase-Locked Loops ...................................................................................................................... 3–10
RAM Blocks ..................................................................................................................................... 3–11
HSDI ................................................................................................................................................. 3–13
Dedicated Source-Synchronous Circuitry .................................................................................. 3–15
General I/O Power ........................................................................................................................ 3–17
High-Speed Transceiver Blocks ................................................................................................... 3–19