Altera PowerPlay Early Power Estimator - Manual (Page 26)

3–10 UG-FPGAPWRCAL-2.0 Altera Corporation
PowerPlay Early Power Estimator User Guide: Stratix, Stratix GX & Cyclone FPGAs October 2005
PowerPlay Early Power Estimator Input Values
Phase-Locked Loops
Stratix and Stratix GX devices have two types of phase-locked loops
(PLLs): enhanced PLLs and fast PLLs. The Phase-Locked Loops (PLLs)
section in the Stratix and Stratix GX PowerPlay early power estimator is
divided into two sections. Cyclone devices have fast PLLs only.
Each row in the PLLs section represents a PLL in the device. For each
enhanced PLL or fast PLL used, you need to enter the maximum output
clock frequency for that PLL.
Table 3–4 describes the values that are
entered in the Phase-Locked Loops (PLLs) section of the PowerPlay early
power estimator.
Figure 3–10 shows an example of the PLL Usage summary in the
Quartus II software Compilation Report for a design targeting a Stratix
device. The Compilation Report provides the output frequency for each
PLL clock output. You only need to enter in the maximum output
frequency for that PLL into the PowerPlay early power estimator.
Figure 3–11 shows the Stratix device PowerPlay early power estimator
and the estimated power consumed by the enhanced PLL and the fast
PLL used in this example.
Table 3–4. Phase-Locked Loops (PLLs) Section Information
Column Heading Description
PLLs Enter a name for the PLL in this column. This is an optional value.
f
M A X
(MHz) The maximum PLL clock output frequency for this PLL. This value is limited by the maximum
PLL output clock frequency specification for the device family.