Zilog Z80180 - Manual (Page 131)

Z8018x
Family MPU User Manual
116
UM005003-0703
The key functions for ASCI on Z80180, Z8S180 and Z8L180 class
processors are listed below. Each channel is independently
programmable.
•
Full-duplex communication
•
7- or 8-bit data length
•
Program controlled 9th data bit for multiprocessor communication
•
1 or 2 stop bits
•
Odd, even, no parity
•
Parity, overrun, framing error detection
•
Programmable baud rate generator, /16 and /64 modes
•
Modem control signals – Channel 0 contains DCD0, CTS0 and RTS0;
Channel 1 contains CTS1
•
Programmable interrupt condition enable and disable
•
Operation with on-chip DMAC
ASCI Block Diagram for the Z8S180/Z8L180-Class
Processors
Figure 52 illustrates the ASCI block diagram.