Zilog Z80180 - Manual (Page 211)

Z8018x
Family MPU User Manual
196
UM005003-0703
54 t
Ef
Enable Fall Time — 10 — 10 ns
55 t
TOD
PHI Fall to Timer Output Delay — 75 — 50 ns
56 t
STDI
CSI/O Transmit Data Delay Time
(Internal Clock Operation) — 2 — 2 tcyc
57 t
STDE
CSI/O Transmit Data Delay Time
(External Clock Operation) — 7.5 t
CY
C
+75
— 75 t
CYC
+60
ns
58 t
SRSI
CSI/O Receive Data Set-up Time
(Internal Clock Operation) 1 — 1 — tcyc
59 t
SRHI
CSI/O Receive Data Hold Time
(Internal Clock Operation) 1 — 1 — tcyc
60 t
SRSE
CSI/O Receive Data Set-up Time
(External Clock Operation) 1 — 1 — tcyc
61 t
SRHE
CSI/O Receive Data Hold Time
(External Clock Operation) 1 — 1 — tcyc
62 t
RES
RESET Set-up Time to PHI Fall 40 — 25 — ns
63 t
REH
RESET Hold Time from PHI Fall 25 — 15 — ns
64 t
OSC
Oscillator Stabilization Time — 20 — 20 ns
65 t
EXR
External Clock Rise Time (EXTAL) — 5 — 5 ns
66 t
EXF
External Clock Fall Time (EXTAL) — 5 — 5 ns
67 t
RR
RESET Rise Time — 50 — 50 ms
68 t
RF
RESET Fall Time — 50 — 50 ms
Table 31. Z8S180 AC Characteristics (Continued) V
DD
= 5V ±10% or
V
DD
= 3.3V ±10%; 33-MHz Characteristics Apply Only to 5V
Operation
No. Symbol Item
Z8S180—20
MHz
Z8S180—33
MHz
Unit Min Max Min Max