Zilog Z80180 User Manual
Page 68
Z8018x
Family MPU User Manual
UM005003-0703
53
CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only)
Bit
7
6
5
4
3
2
1
0
Bit/Field
Clock
Divide
STAND
BY/
IDLE
Enable
BREXT
LNPHI
STAND
BY/
IDLE
Enable
LNIO
LNCPU
CTL
LNAD/
DATA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
R/W
Value Description
7
Clock
Divide
R/W
0
1
XTAL/2
XTAL/1
6
STANDBY
/IDLE Mode
R/W
00
01
10
11
In conjunction with Bit 3
No STANDBY
IDLE after SLEEP
STANDBY after SLEEP
STANDBY after SLEEP 64 Cycle Exit (Quick
Recovery)
5
BREXT
R/W
0
1
Ignore BUSREQ in STANDBY/IDLE
STANDBY/IDLE exit on BUSREQ
4
LNPHI
R/W
0
1
Standard Drive
33% Drive on EXTPHI Clock
3
STANDBY
/IDLE Mode
R/W
00
01
10
11
In conjunction with Bit 6
No STANDBY
IDLE after SLEEP
STANDBY after SLEEP
STANDBY after SLEEP 64 Cycle Exit (Quick
Recovery)