Zilog Z80180 - Manual (Page 46)

Z8018x
Family MPU User Manual
UM005003-0703
31
Also, the WAIT input is ignored during RESET. For example, if RESET
is detected while the Z8X180 is in a Wait State (TW), the Wait Stated
cycle in progress is aborted, and the RESET sequence initiated. Thus,
RESET has higher priority than WAIT.
HALT and Low Power Operation Modes (Z80180-Class
Processors Only)
The Z80180 can operate in two different modes:
•
HALT mode
•
IOSTOP mode
and two low-power operation modes:
•
SLEEP
•
SYSTEM STOP
In all operating modes, the basic CPU clock (XTAL, EXTAL) must
remain active.
HALT Mode
HALT mode is entered by execution of the HALT instruction (Op Code
76H
) and has the following characteristics:
•
The internal CPU clock remains active
•
All internal and external interrupts can be received
•
Bus exchange (BUSREQ and BUSACK) can occur
•
Dynamic RAM refresh cycle (RFSH) insertion continues at the
programmed interval
•
I/O operations (ASCI, CSI/O and PRT) continue
•
The DMAC can operate