SMC Networks ARM PL241 - Manual (Page 19)

Introduction
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-5
1.2 Supported devices
The SMC supports SRAM/NOR, see SMC on page 1-4. The Release Note provides a
specific list of memory devices tested with each configuration.
Some memory devices or series of memory devices have specific requirements:
Intel W18 series NOR FLASH, for example 28f128W18td
These devices, when in synchronous operation, use a WAIT pin.
However non-array operations when in synchronous mode do not use the
WAIT pin and it is always asserted. The controller cannot differentiate
between array and non-array accesses and therefore cannot support these
non-array accesses.
Therefore, W18 devices can only carry out non-array operations such as
Read Status in asynchronous modes of operation.
Cellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb_701_1us
You can program these devices using a CRE pin or by software access.
Whenever you program these devices through software access, using a
sequence of two reads followed by two writes, ensure that the third
access, that is, the first write is a
CE# controlled write.
SMC only does WE# controlled writes. This is to simplify the design of the
SMC by having fewer timing registers and simpler timing controls.
Therefore, you can only program these devices by using the CRE pin
method of access.
Note
Because the memory controller maps INCR transfers into INCR4 transfers, it does not
support memory mapped FIFO components.