SMC Networks ARM PL241 - Manual (Page 81)

Programmer’s Model
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-21
SMC Peripheral Identification Register 1
The smc_periph_id_1 Register is hard-coded and the fields within the register indicate
the value. Table 3-16 lists the register bit assignments.
SMC Peripheral Identification Register 2
The smc_periph_id_2 Register is hard-coded and the fields within the register indicate
the value. Table 3-17 lists the register bit assignments.
SMC Peripheral Identification Register 3
The smc_periph_id_3 Register is hard-coded and the fields within the register indicate
the value of
0x0 . Table 3-18 lists the register bit assignments.
Table 3-16 smc_periph_id_1 Register bit assignments
Bits Name Function
[31:8] - Reserved, read undefined
[7:4] designer_0 These bits read back as 0x1
[3:0] part_number_1 These bits read back as 0x3
Table 3-17 smc_periph_id_2 Register bit assignments
Bits Name Function
[31:8] - Reserved, read undefined
[7:4] revision These bits read back as 0x3
[3:0] designer_1 These bits read back as 0x4
Table 3-18 smc_periph_id_3 Register bit assignments
Bits Name Function
[31:8] - Reserved, read undefined.
[7:1] - Reserved for future use. Read undefined.
[0] integration_cfg When set, the integration test register map at address offset 0xE00 is present for reading and
writing. If clear, the integration test registers have not been implemented.