Table 2-14, Table 2-15, Figure 2-20 – SMC Networks ARM PL241 User Manual
Page 54: Synchronous burst read in multiplexed-mode -34
Functional Overview
2-34
Copyright © 2006 ARM Limited. All rights reserved.
ARM DDI 0389B
Synchronous burst read in multiplexed-mode
Table 2-14 and Table 2-15 list the smc_opmode0_<0-3> and SRAM Register settings.
Figure 2-20 shows the same synchronous read burst transfer as Figure 2-19 on
page 2-33, but in multiplexed-mode.
Figure 2-20 Synchronous burst read in multiplexed-mode
Table 2-14 Synchronous burst read in multiplexed-mode opmode chip register
settings
Field
mw
rd_sync
rd_bl
wr_sync
wr_bl
baa
adv
bls
ba
Value
-
b1
<burst length>
-
-
-
-
-
-
Table 2-15 Synchronous burst read in multiplexed-mode read SRAM cycles
register settings
Field
t_rc
t_wc
t_ceoe
t_wp
t_pc
t_tr
Value
b0100
-
b010
-
-
-
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