SMC Networks ARM PL241 - Manual (Page 72)

Programmer’s Model
3-12 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
3.3.7 SMC Set Opmode Register at 0x1018
This register is the holding register for the smc_opmode0_<n> working registers. The
write-only smc_set_opmode Register cannot be written to in either the Reset or
Low-power state. Figure 3-12 shows the register bit assignments.
Note
Table 3-8 on page 3-13 describes register holding, see Memory manager operation on
page 2-22 for more information.
Figure 3-12 smc_set_opmode Register bit assignments
       
VHWBPZ
VHWBUGBV\QF
VHWBUGBEO
VHWBZUBV\QF
VHWBZUBEO
8QGHILQHG

VHWBEOV
VHWBDGY
VHWBEDD
  
VHWBEXUVWBDOLJQ