Smc primecell identification register 0, Smc primecell identification register 1, Table 3-20 – SMC Networks ARM PL241 User Manual
Page 83: Smc_pcell_id_0 register bit assignments -23, Table 3-21, Smc_pcell_id_1 register bit assignments -23
Programmer’s Model
ARM DDI 0389B
Copyright © 2006 ARM Limited. All rights reserved.
3-23
The following sections describe the smc_pcell_id Registers:
•
SMC PrimeCell Identification Register 0
•
SMC PrimeCell Identification Register 1
•
SMC PrimeCell Identification Register 2 on page 3-24
•
SMC PrimeCell Identification Register 3 on page 3-24.
Note
These registers cannot be read in the Reset state.
SMC PrimeCell Identification Register 0
The smc_pcell_id_0 Register is hard-coded and the fields within the register indicate
the value. Table 3-20 lists the register bit assignments.
SMC PrimeCell Identification Register 1
The smc_pcell_id_1 Register is hard-coded and the fields within the register indicate
the value. Table 3-21 lists the register bit assignments.
Table 3-20 smc_pcell_id_0 Register bit assignments
Bits
Name
Function
[31:8]
-
Reserved, read undefined
[7:0]
smc_pcell_id_0
These bits read back as
0x0D
Table 3-21 smc_pcell_id_1 Register bit assignments
Bits
Name
Function
[31:8]
-
Reserved, read undefined
[7:0]
smc_pcell_id_1
These bits read back as
0xF0