SMC Networks ARM PL241 - Manual (Page 5)

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. v
List of Tables
PrimeCell AHB SRAM/NOR Memory Controller
(PL241) Technical Reference Manual
Change History ............................................................................................................. ii
Table 2-1 Static memory clocking options ............................................................................... 2-12
Table 2-2 Asynchronous read opmode chip register settings ................................................. 2-28
Table 2-3 Asynchronous read SRAM cycles register settings ................................................. 2-28
Table 2-4 Asynchronous read in multiplexed-mode opmode chip register settings ................ 2-29
Table 2-5 Asynchronous read in multiplexed-mode SRAM cycles register settings ............... 2-29
Table 2-6 Asynchronous write opmode chip register settings ................................................. 2-30
Table 2-7 Asynchronous write SRAM cycles register settings ................................................ 2-30
Table 2-8 Asynchronous write in multiplexed-mode opmode chip register settings ................ 2-31
Table 2-9 Asynchronous write in multiplexed-mode SRAM cycles register settings ............... 2-31
Table 2-10 Page read opmode chip register settings ................................................................ 2-31
Table 2-11 Page read SRAM cycles register settings ............................................................... 2-31
Table 2-12 Synchronous burst read opmode chip register settings .......................................... 2-32
Table 2-13 Synchronous burst read SRAM cycles register settings ......................................... 2-32
Table 2-14 Synchronous burst read in multiplexed-mode opmode chip register settings ......... 2-34
Table 2-15 Synchronous burst read in multiplexed-mode read SRAM cycles register settings 2-34
Table 2-16 Synchronous burst write opmode chip register settings .......................................... 2-35
Table 2-17 Synchronous burst write SRAM cycles register settings ......................................... 2-35
Table 2-18 Synchronous burst write in multiplexed-mode opmode chip register settings ......... 2-36
Table 2-19 Synchronous burst write in multiplexed-mode SRAM cycles register settings ........ 2-36
Table 2-20 Synchronous read and asynchronous write opmode chip register settings ............ 2-37