Table 2-4, Table 2-5, Figure 2-14 – SMC Networks ARM PL241 User Manual
Page 49: Asynchronous read -29, Figure 2-15, Asynchronous read in multiplexed-mode -29
Functional Overview
ARM DDI 0389B
Copyright © 2006 ARM Limited. All rights reserved.
2-29
Figure 2-14 Asynchronous read
Asynchronous read in multiplexed-mode
Table 2-4 and Table 2-5 list the smc_opmode0_<0-3> and SRAM Register settings.
Figure 2-15 shows a single asynchronous read transfer in multiplexed-SRAM mode,
with t
RC
= 7, and t
CEOE
= 5.
Figure 2-15 Asynchronous read in multiplexed-mode
VPFBPFON
VPFBFVBQB> @
VPFBRHBQB
VPFBDGGB> @
VPFBGDWDBLQB> @
UHDGBGDWD
$
'
W
5&
W
&(2(
'
Table 2-4 Asynchronous read in multiplexed-mode opmode chip register settings
Field
mw
rd_sync
rd_bl
wr_sync
wr_bl
baa
adv
bls
ba
Value
-
b0
b000
-
-
-
b1
-
-
Table 2-5 Asynchronous read in multiplexed-mode SRAM cycles register settings
Field
t_rc
t_wc
t_ceoe
t_wp
t_pc
t_tr
Value
b0111
-
b101
-
-
-
VPFBPFON
UHDGBGDWD
VPFBFVBQB
VPFBRHBQB
VPFBDGYBQB
VPFBGDWDBHQB
VPFBGDWDBRXWB
W
&(2(
W
5&
$
'
'