SMC Networks ARM PL241 - Manual (Page 68)

Programmer’s Model
3-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
3.3.3 SMC Set Configuration Register at 0x1008
The write-only smc_memc_cfg_set Register enables the memory controller to be
changed to Low-power state, and interrupts enabled. This register cannot be written to
in the Reset state. Figure 3-8 shows the register bit assignments.
Figure 3-8 smc_memc_cfg_set Register bit assignments
[3:2] memory_chips0 Returns the number of different chip selects that the memory interface 0 supports:
b00 = 1 chip
b01 = 2 chips
b10 = 3 chips
b11 = 4 chips.
[1:0] memory_type0 Returns the memory interface 0 type:
b00 = reserved
b01 = SRAM
b10 = NAND
b11 = reserved.
Table 3-3 smc_memif_cfg Register bit assignments (continued)
Bits Name Function
    
LQWBHQDEOH
5HVHUYHG
ORZBSRZHUBUHT
8QGHILQHG