SMC Networks ARM PL241 - Manual (Page 80)

Programmer’s Model
3-20 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
Figure 3-18 shows the correspondence between bits of the smc_ periph_id registers and
the conceptual 32-bit Peripheral ID Register.
Figure 3-18 smc_periph_id Register bit assignments
The following section describe the smc_periph_id Registers
• SMC Peripheral Identification Register 0
• SMC Peripheral Identification Register 1 on page 3-21
• SMC Peripheral Identification Register 2 on page 3-21
• SMC Peripheral Identification Register 3 on page 3-21.
SMC Peripheral Identification Register 0
The smc_periph_id_0 Register is hard-coded and the fields within the register indicate
the value. Table 3-15 lists the register bit assignments.
           
 
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Table 3-15 smc_periph_id_0 Register bit assignments
Bits Name Function
[31:8] - Reserved, read undefined
[7:0] part_number_0 These bits read back as 0x52