SMC Networks ARM PL241 - Manual (Page 97)

Signal Descriptions
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-3
A.2 Clocks and resets
Table A-1 lists the clock and reset signals.
Table A-1 Clocks and resets
Name Type
Source/
destination
Description
hclk Input Clock source AHB clock
hresetn Input Reset source AHB clock domain reset
smc_aclk Input Clock source SMC AHB clock
smc_mclk0 Input Clock source SMC memory clock
smc_mclk0n Input Clock source SMC inverted memory clock
smc_mreset0n Input Reset source SMC memory clock domain reset