Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 23)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 23
Product Specification
EAR
LY
ACCESS
PLB PCI Bridge Register Descriptions
The PLB PCI Bridge contains addressable registers for read/write operations as shown in Table 5 . The
base address for these registers is set by the base address parameter (C_BASEADDR). The address of
each register is then calculated by an offset to the base address as shown in
Table 5 . Registers that reside
in the user area of the PCI configuration header are mirrored in the IPIF register space as read-only
registers; this is included for debug utility.
The registers that exist in a given PLB PCI bridge depend on
the configuration of the bridge.
Table 5: PLB PCI Bus Interface Registers
Register Name PLB Address Access
Device Interrupt Status Register (ISR) C_BASEADDR + 0x00 Read/TOW
Device Interrupt Pending Register (IPR) C_BASEADDR + 0x04 Read/Write
Device Interrupt Enable Register (IER) C_BASEADDR + 0x08 Read/Write
Device Interrupt ID (IID) C_BASEADDR + 0x18 Read
Global Interrupt Enable Register (GIE) C_BASEADDR + 0x1C Read/Write
Bridge Interrupt Register C_BASEADDR + 0x20 Read/TOW
Bridge Interrupt Enable Register C_BASEADDR + 0x28 Read/Write
Reset Module C_BASEADDR + 0x80 Read/Write
Configuration Address Port C_BASEADDR + 0x10C Read/Write
Configuration Data Port C_BASEADDR + 0x110 Read/Write
Bus Number/Subordinate Bus Number C_BASEADDR + 0x114 Read/Write
IPIFBAR2PCIBAR_0 high-order bits C_BASEADDR + 0x180 Read/Write
IPIFBAR2PCIBAR_1 high-order bits C_BASEADDR + 0x184 Read/Write
IPIFBAR2PCIBAR_2 high-order bits C_BASEADDR + 0x188 Read/Write
IPIFBAR2PCIBAR_3 high-order bits C_BASEADDR + 0x18C Read/Write
IPIFBAR2PCIBAR_4 high-order bits C_BASEADDR + 0x190 Read/Write
IPIFBAR2PCIBAR_5 high-order bits C_BASEADDR + 0x194 Read/Write
Host Bridge device number C_BASEADDR + 0x198 Read/Write
1101 Dual Address Cycle Ignore No
1110 Memory Read Line Yes No
1111 Memory Write Invalidate Yes No
Table 4: Supported PCI Bus Commands