Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 53)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 53
Product Specification
EAR
LY
ACCESS
NET "*/RST_N" IOBDELAY = BOTH ;
NET "*/AD<*>" IOBDELAY = BOTH ;
NET "*/CBE<*>" IOBDELAY = BOTH ;
NET "*/REQ_N" IOBDELAY = BOTH ;
NET "*/GNT_N" IOBDELAY = BOTH ;
NET "*/PAR" IOBDELAY = BOTH ;
NET "*/IDSEL" IOBDELAY = BOTH ;
NET "*/FRAME_N" IOBDELAY = BOTH ;
NET "*/IRDY_N" IOBDELAY = BOTH ;
NET "*/TRDY_N" IOBDELAY = BOTH ;
NET "*/DEVSEL_N" IOBDELAY = BOTH ;
NET "*/STOP_N" IOBDELAY = BOTH ;
NET "*/PERR_N" IOBDELAY = BOTH ;
NET "*/SERR_N" IOBDELAY = BOTH ;
NET "*/PCI_INTA" IOBDELAY = BOTH ;
TNM constraints must be defined as specified in v3 Design Guide and v3.0 core ucf-files. These
parameters are automatically set in the normal EDK tool flow, but can be included in the system
top-level ucf-file. For alternative tool flows, the settings are shown below. When the complete set of
constraints is used, the PCI clock must be a PAD input which is the required clock routing for all v3.0
core implementations. The EDK flow checks if the PCI clock is a PAD input and if it is, then the OFFSET
constraints shown below are includes in the bridge ngc-file.
##########################################################################
# Time Specs
##########################################################################
#
# Important Note: The timespecs used in this section cover all possible
# paths. Depending on the design options, some of the timespecs might
# not contain any paths. Such timespecs are ignored by PAR and TRCE.
#
# 1) Clock to Output = 11.000 ns
# 2) Setup = 7.000 ns
# 3) Grant Setup = 10.000 ns
# 4) Datapath Tristate = 28.000 ns
# 5) Period = 30.000 ns
#
# Note: Timespecs are derived from the PCI Bus Specification. Use of
# offset constraints allows the timing tools to automatically include
# the clock delay estimates. These constraints are for 33 MHz operation.
#
# The following timespecs are for setup.
#
TIMEGRP "PCI_PADS_D" OFFSET=IN 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP
"ALL_FFS" ;
TIMEGRP "PCI_PADS_B" OFFSET=IN 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP
"ALL_FFS" ;
TIMEGRP "PCI_PADS_P" OFFSET=IN 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP
"ALL_FFS" ;
TIMEGRP "PCI_PADS_C" OFFSET=IN 7.000 VALID 7.000 BEFORE "PCI_CLK" TIMEGRP
"ALL_FFS" ;
#
# The following timespecs are for clock to out where stepping is not used.