Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 55)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 55
Product Specification
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one IDELAYCTRl without LOC constraints, the tools will replicate the primitive throughout the design.
Replicating the primitive has the undesirable results of higher power consumption, higher power
consumption, utilization of more global clock resources, and greater use of routing resources. To
prevent these undesirable results, a procedure is described in the next paragraph for instantiating the
IDELAYCTRLs. See the
Virtex-4 User Guide discussion of IDELAYCTRL usage and design guidance
for more details on IDELAYCTRL and usage. Tools beyond ISE 7.1 might handle IDELAYCTRL
instantiation differently.
It turns out that the number of signals in the PCI protocol requires at least two IDELAYCTRL primitives
when implemented in the Virtex-4 architecture. The actual number depends on the pinout defined by
the user. To avoid the undesirable results noted above, the LogiCORE v3 PCI core standalone core is
fixed to use two IDELAYCTRL instantiations and prescribes pinouts that require only two
IDELAYCTRL primitives. To provide more flexibility to the user, the OPB PCI Bridge allows specifying
the number of IDELAYCTRL primitives from two to six; this is set at build time by set the parameter
C_NUM_IDELAYCTRL. However, it might be difficult to meet timing when the pinout is spread out to
require four to six IDELAYCTRL primitives and it is recommended to use a PCI pinout packed together
enough to require only two IDELAYCTRL primitives. See the
Virtex-4 User Guide discussion of
IDELAYCTRL usage and design guidance or the Virtex -4 Library Guide for IDELAYCTRL primitives
for more details.
When more than one IDELAYCTRL is instantiated, the ISE 8.1 tools require LOC constraints on each
IDELAYCTRL instantiation. A failure in MAP will occur if the LOC constraints are not provided. The
FPGA Editor tool can be helpful to determine IDELAYCTRL LOC coordinates for the user's pinout. The
syntax for the ucf-file LOC constraints is shown in the example below where the instance name in the
OPB PCI Bridge for each IDELAYCTRL is XPCI_IDC0 to XPCI_IDCN where N is the
C_NUM_IDELAYCTRL-1. The user need only include an LOC entry for each instance used in the
system design and not for all possible six IDELAY controllers. For each entry, include the LOC
coordinates for the part and pinout in the design. The example below is for a design that uses 2
IDELAYCTRL primitives.
This approach allows users to use the constraint LOC coordinates directly from the LogiCORE v3.0
core ucf-generator. Note that the ucf-file generator prescribes I/O pin layout that only uses two
IDELAYCTRL primitives. The example below is for a system with two IDELAYCTRL primitives with
example only coordinates. Depending on the user’s pinout, more IDELAYCTRLs might be needed.
INST *XPCI_IDC0 LOC=IDELAYCTRL_X2Y5;
INST *XPCI_IDC1 LOC=IDELAYCTRL_X2Y6;
An optional method for setting of LOC constraints is to use the C_IDELAYCTRL_LOC parameter. This
parameter when properly set will generate constraints in the bridge core ucf-file that is combined with
the opb_pci bridge ngc-file during normal EDK tool flow. Note that if the LOC constraints are set in the
system top-level ucf-file, then this parameter is has no effect for either case of it being properly set or set
to default (i.e., NOT_SET). This is because the system top-level ucf-file overrides all core level ucf
constraints. However, if it is not set, then a warning that it is not set is asserted early in the EDK tool
flow for the tool options, generate netlist, generate bitstream, and other tool options that would
invoke synthesis of the opb_pci bridge. If the system top-level ucf-file does include the LOC
constraints, then this warning can be ignored. With EDK 8.1 tools, MAP will fail if the LOC coordinates
are not provided by at least one of the methods. An example of the syntax for the
C_IDELAYCTRL_LOC parameter is shown below.