Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 43)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 43
Product Specification
EAR
LY
ACCESS
If the PLB clock is slower, the data flow is a series of PCI transactions that are terminated by the PLB
PCI Bridge as a disconnect without data after the number of data phases specified by
C_TRIG_PCI_DATA_XFER_OCC_LEVEL, or a few more depending on the PLB slave throttling
characteristics and relative clock rates. This is because the PLB slave does not supply data fast enough
for execution of read multiple command with single PCI clock cycle data phases. Single clock cycle data
phases are required because the v3.0 core cannot throttle the data. The PLB PCI Bridge can throttle the
first data transfer to PCI until a predefined number of words are available in the FIFO which is set by
C_TRIG_PCI_DATA_XFER_OCC_LEVEL. This parameter will differ for different clock rates and must
be adjusted to insure that PCI spec is not violated. One PCI specification that can be violated is the
maximum allowed throttling of the first data transfer.
Abnormal Terminations
1. If an address parity error is detected, the v3.0 core will either claim the transaction and issue a
Target Abort, or will not claim the transaction and a Master Abort will occur (see v3.0 core
documentation). When a Target Abort is issued, the v3.0 core asserts SERR_N, if enabled.
2. If SERR_N is asserted by a remote agent in a data phase on either a single or a burst transfer, it is left
to the PCI initiator to report the error and initiate any recovery effort that may be needed. The PLB
PCI Bridge disconnects with data as soon as possible and any data left is the internal FIFOs are
discarded.
3. If on either a single or a burst transfer a PERR error is detected during a data phase, the PLB PCI
Bridge does nothing. Whether the PCI initiator continues or not is initiator dependent.
4. If either a read or a read multiple command is performed and a PLB rearbitrate is asserted by the
PLB slave on the first request for data, the PLB PCI Bridge commands the v3.0 core to disconnect
without data (i.e., PCI retry), and the PCI initiator is required to retry the transaction.
5. If a PLB slave rearbitrate occurs on the second or subsequent retried read request during a read
multiple command, the PLB PCI Bridge automatically retries the PLB request and attempts to keep
the fifo full. If the fifo is emptied before a retry is successful, the bridge disconnects without data
when the fifo is empty.
6. If a PLB Sl_MErr occurs during either a read or a read multiple command, the PLB PCI Bridge
commands the v3.0 core to immediately disconnect without data and the PCI interrupt is strobed.
Sl_MErr can be asserted due to an address phase timeout or a slave assertion of the error signal.
7. If during a read multiple command a PLB slave asserts PLB_MRdBTerm which terminates the PLB
burst read, the PLB PCI Bridge automatically retries the PLB request and attempts to keep the fifo
full. If the fifo is emptied before a retry is successful, the bridge disconnects without data when the
fifo is empty.
8. On a read multiple command transaction, in which the bridge prefectches data, the address will not
prefetch beyond the valid range. The IP Master in the bridge will attempt to fill the FIFO with data
from addresses up to the limit of the valid range which is defined by the PCIBAR length parameter.
All transactions on the PLB will be burst reads of the PLB slave that are terminated by the slave,
terminated by the FIFO being filled, or terminated when the last address of the defined range is
reached. This response is adopted rather than a target abort which is an option per PCI
specification. Recall that the v3.0 core cannot throttle data as a target after the first data phase. As
data is read by the PCI agent, a disconnect will occur when the FIFO is emptied.
Table 19 summarizes most PLB slave abnormal conditions in a memory read command and how the
response is translated to the PCI initiator.