Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 3)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 3
Product Specification
EAR
LY
ACCESS
default in all transfers. Address translation is performed by high-order bit substitution.
High-order bit definition is defined only by parameters
• Registers include
- Interrupt and interrupt enable registers at different hierarchal levels
- Reset
- Configuration Address Port, Configuration Data Port and Bus Number/Subordinate Bus
Number
- High-order bits for PLB to PCI address translation
- Bridge Device number on PCI bus
• PLB-side Interrupts include
- PLB Master Read SERR and PERR
- PLB Master Read Target Abort
- PLB Master Write SERR and PERR
- PLB Master Write Target Abort
- PLB Master Write Master Abort
- PLB Master Burst Write Retry and Retry Disconnect
- PLB Master Burst Write Retry Timeout
- PCI Initiator Read and Write SERR
• Asynchronous FIFOs with backup capability
• Synchronization circuits for signals that cross time-domain boundaries
• Responds to the PCI latency timer
• Completes posted write operations prior to initiating new operations
• Signal set required for integrating a PCI bus arbiter in the FPGA with the PLB PCI bridge is
available at the top-level of the PLB PCI bridge module. The signal set includes PCLK, RST_N,
FRAME_I, REQ_N_toArb and IRDY_I
• Supports PCI clock generated in FPGA
• Parameterized control of IO-buffer insertion of INTR_A and REQ_N IO-buffers
• All address translations performed by high-order bit substitution. The number of bits substituted
depends on the address range
- Parameterized selection of IPIF BAR high-order bits defined by programmable registers for
dynamic translation operation or by parameters for reduced resource utilization
• Parameterized selection of device ID number (when configuration functionality is included)
defined by a programmable register for dynamic device number definition or by parameter to
reduce resource utilization
• The PLB PCI bridge does not have an integral DMA
• Input signal to provide the means to asynchronous asset INTR_A from a user supplied register (i.e.,
a PLB GPIO). The signal is Bus2PCI_INTR is an active high signal
• PCI Monitor output port to monitor PCI bus activity