Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 57)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 57
Product Specification
EAR
LY
ACCESS
the ucf-file in the implementation directory of the bridge directory to verify that the constraints are
included. Alternatively, the user can include all constraints in the top-level ucf-file. When the
constraints are included in both the top-level ucf-file and the bridge ngc-file (via the bridge directory
ucf-file), then the top-level ucf-file overrides any conflicting constraints in the bridge ngc-file.
Device Utilization and Performance Benchmarks
Because the PLB PCI Bridge is a module that will be used with other design pieces in the FPGA, the
utilization and timing numbers reported in this section are just estimates. As the PLB PCI Bridge is
combined with other pieces of the FPGA design, the utilization of FPGA resources and timing of the
PLB PCI Bridge design will vary from the results reported here.
In order to analyze the PLB PCI Bridge timing within the FPGA, a design was created that instantiated
the PLB PCI bridge with the parameters set as outlined in
Table 25 . The data is shown for a Virtex-II Pro
device; for Virtex-4 devices and an additional GCLK is required for the RCLK 200 MHz signal.
Table 25: PLB PCI Bridge FPGA Performance and Resource Utilization Benchmarks
Parameter Values Device Resources f
MAX
Configuration
Description
C_
IPIFBAR_
NUM
C_PCI_BAR_NUM
C_I
P
IF
2PCI
_F
IF
O_
ABUS_W
IDT
H
C_PCI
2
IP
IF
_F
IF
O_
ABUS_W
IDT
H
C
_
INCLUDE_
P
CI_
CON
FIG
Slices
Slice Fl
ip- Fl
ops
4- inpu
t LUTs
# BR
AM
# GC
LK
MHz
Total (with BarOffset and
DevNumregs)
6 3 9 1 3336 2961 3868 8 2 >100
Total (with BarOffset and
DevNumregs)
6 3 5 1 3163 2729 3695 8 2 >100
Total (without BarOffset
and DevNum regs)
6 3 9 1 3163 2805 3615 8 2 >100
Total (without BarOffset
and DevNum regs)
6 3 5 1 2976 2573 3442 8 2 >100
Total (with BarOffset and
DevNum regs)
4 2 9 1 3181 2851 3667 8 2 >100
Total (without BarOffset
and DevNum regs)
4 2 9 0 2962 2684 3352 8 2 >100
Notes:
1. These benchmark designs contain only the PLB PCI Bridge with registered inputs/outputs with any additional
logic. Benchmark numbers approach the performance ceiling rather that representing performance under
typical user conditions.
2. N/A - Not applicable