Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 40)

PLB PCI Full Bridge (v1.00a)
40 www.xilinx.com DS508 March 21, 2006
Product Specification
EARL
Y ACCESS
transaction. The PLB PCI Bridge performs retries up to a parameterized number of times as
described earlier for the condition of disconnects with/without data. A time-out cannot occur
during a single transfer because the v3.0 core requires completion of one data transfer after the
latency timer expires.
• If a target abort occurs during either a single or burst write operation, the PLB Master Write Target
Abort interrupt is asserted. If a burst write is in progress, Sl_MErr is asserted with Sl_wrDAck.
Recall that a target abort often indicates that the target cannot proceed with subsequent
transactions; this is expected to be a major failure most likely requiring a reset.
• If the remote PLB master burst writes beyond a valid address range, the PLB IPIF will accept the
data because the PLB IPIF does not check for valid address with data phase. However, the PLB PCI
Bridge will not accept the data and the data will remain buffered in the PLB IPIF. In this situation, a
PLB IPIF timeout will occur for each double word buffered in the IPIF. Because the write is posted,
the PLB transaction has completed on the PLB and Slv_MErr is not asserted. When each timeout
occurs, the double word presented at the IPIC is discarded and the next double word is presented
at the IPIC. After the last timeout occurs and the last valid data is transferred successfully to the
PCI target, the bridge is available for a new write transaction.
Table 18 summarizes the abnormal conditions that a PCI target can respond with and how the response
is translated to the PLB master.
Table 18: Response of PLB Master/v3.0 Initiator write to a remote PCI target with abnormal condition on
PCI bus
Abnormal
condition
Single transfer
Burst
(PLB_wrBurst asserted)
SERR (includes
parity error on
address phase)
PLB Master Write SERR interrupt
asserted
If transfer is in progress, Sl_MErr is asserted with
Sl_wrDAck. PLB Master Write SERR interrupt
asserted
PLB PCI Bridge
Master abort (no
PCI target
response)
PLB Master Abort Write interrupt
asserted
If transfer is in progress, Sl_MErr is asserted with
Sl_wrDAck. PLB Master Abort Write interrupt
asserted and FIFO flushed.
Target
disconnect
without data
(PCI Retry)
Automatically retried a parameterized
number of times. If the last of the PCI
write command retries fails due to a PCI
Retry, the PLB Master Write Retry
interrupt is asserted.
Automatically retried a parameterized number of
times. If the last of the PCI write command retries
fails due to a PCI Retry, the PLB Master Write
Retry interrupt is asserted.
Target
disconnect
without data
(after one
completed data
phase)
N/A
Automatically retried a parameterized number of
times. If the last of the PCI write command retries
fails due to a Disconnect with(out) Data, the PLB
Master Write Retry Disconnect interrupt is
asserted.
Target
disconnect with
data
Completes
PERR
Transaction completes and PLB Master
Write PERR interrupt asserted
PLB Master Write PERR interrupt asserted. If the
burst write is still in progress, Sl_MErr is asserted
with Sl_wrDAck. FIFO is flushed.