Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 54)

PLB PCI Full Bridge (v1.00a)
54 www.xilinx.com DS508 March 21, 2006
Product Specification
EARL
Y ACCESS
#
TIMEGRP "PCI_PADS_D" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ;
TIMEGRP "PCI_PADS_B" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ;
TIMEGRP "PCI_PADS_P" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ;
TIMEGRP "PCI_PADS_C" OFFSET=OUT 11.000 AFTER "PCI_CLK" TIMEGRP "ALL_FFS" ;
#
# The following timespecs are for clock to out where stepping is used.
#
TIMEGRP "PCI_PADS_D" OFFSET=OUT 28.000 AFTER "PCI_CLK" TIMEGRP "SLOW_FFS" ;
TIMEGRP "PCI_PADS_B" OFFSET=OUT 28.000 AFTER "PCI_CLK" TIMEGRP "SLOW_FFS" ;
TIMEGRP "PCI_PADS_P" OFFSET=OUT 28.000 AFTER "PCI_CLK" TIMEGRP "SLOW_FFS" ;
Target Technology
The intended target technology is for devices: QPro-R, Virtex-II, QPro Virtex-II, Spartan-II, Spartan-IIE,
Virtex, Virtex-II, Virtex-E, Virtex-II Pro, and Virtex-4.
Virtex-4 Support
To meet PCI specification setup and hold times with the Virtex-4 architecture, it is necessary to insert an
IDELAY primitive between the pad and I/O buffer of most PCI signals and to include additional
constraints in the ucf-file. When IDELAY primitives are used in the mode required by the LogiCORE
v3.0 core, IDELAYCTRL (idelay controllers) are required. Also required is a 200 MHz reference clock
supplied by the user which is used by both IDELAY and IDELAYCTRL primitives. Note that these
primitives are only required for Virtex-4 architecture. The additional constraints are discussed after the
discussion of primitives specific to Virtex-4 devices.
The 200 MHz clock is input to port RCLK and must be driven by a global buffer. If the architecture is
not off the Virtex-4 platform, the port does not connect to anything in the opb_pci bridge, and it might
be omitted from the MHS-file. This allows upgrading to v1.02.a from v1.01.a without changing ports.
Recall that v1.01.a does not support the Virtex-4 architecture. It is required that the 200 MHz clock be
stable when OPB_RST is asserted to the OPB PCI Bridge. An unstable clock can result failure of OPB
PCI Bridge operation. The clock source can be an external source or generated with a DCM in the
FPGA. Application Notes and Implementation Guides for the LogiCORE v3.0 core, as well as reference
designs using the OPB PCI Bridge, present options for generating the 200 MHz clock.
IDELAY primitives are instantiated automatically by the bridge when the Virtex-4 C_FAMILY
parameter is set to the Virtex-4 architecure. The EDK tools automatically set this parameter and it can
not be changed by the user. There is a special case to consider for instantiation of IDELAY primitives.
Port GNT_N requires the IDELAY primitive only if the port is connected to a package pin. If GNT_N is
connected to an internal signal (e.g., an FPGA internal arbiter such as pci_arbiter_v1_00_a) or
connected to ground, then an IDELAY primitive is not needed. EDK tools have the system level
information to determine if GNT_N is connected to a pad or has an internal connection. This
accomplished with a tcl-script in the OPB PCI Bridge pcore library that is called by the EDK tools. EDK
tools automatically sets the parameter C_INCLUDE_GNT_DELAY which controls if an IDELAY
primitive is included in the GNT_N signal path. C_INCLUDE_GNT_DELAY defaults to exclude the
IDELAY primitive and must be set by the user if the core is used outside EDK tools with GNT_N
connected to a pin.
IDELAYCTRL primitives are not as automatic in the build procedure. It is required that the user
instantiate the number of IDELAYCTRL primitive needed for their design and to provide LOC
contraints for each IDELAYCTRL. This is required for EDK 8.1 tools because when instantiating only