Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 35)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 35
Product Specification
EAR
LY
ACCESS
mode).
• If the PCI target address space is IO-space, the 2 LSBs are passed unchanged from that presented on
the PLB bus.
If the PLB transaction is not a burst (i.e., PLB_rdBurst is not high), a single PCI transaction (I/O or
Memory Read command) is performed and the PLB transaction is terminated on the first double word
transaction. This results in low data throughput.
If the transaction is a PLB burst transaction (i.e., PLB_rdBurst is high) and the space type is memory, the
PLB PCI Bridge issues a memory read multiple command on the PCI bus and attempts to fill the bridge
PCI2IPIF FIFO. Throttling can be performed by the PLB PCI bridge supplying data to the remote PLB
master by delaying acknowledgements until the data is loaded in the FIFO. All data is transmitted to
the PLB Dbus as soon as it is received. Because the PCI bus is usually slower than the PLB, significant
throttling time can occur. If the PLB PCI Bridge fills the FIFO in the bridge or the latency timer expires,
the PLB PCI Bridge terminates the prefetch read operation. The prefetch read operation can be
terminated by the remote PCI target as well.
The user must specify when the PLB PCI Bridge is to start another prefetch read of the remote PCI
target by setting the paramter C_TRIG_PCI_READ_OCC_LEVEL. This parameter is a number which is
compared to the number of words in the PCI2PLB FIFO. If the number of words in the PCI2PLB FIFO
is less than C_TRIG_PCI_READ_OCC_LEVEL, the PLB PCI Bridge starts prefetch reads of the remote
PCI target. The PLB PCI Bridge determines the address to insure consecutive data is prefetched.
If the PCI2IPIF_FIFO is emptied before more data can be prefetched, the PLB transaction will be
terminated. When the PLB master terminates the transaction with data remaining in the FIFO, the FIFO
is flushed. Because the data is required to be prefetchable, data is not lost when the FIFO is flushed.
Dynamic byte enable is not supported in Xilinx PLB burst operations and is not supported in the PLB
Master read of a PCI target. All byte enable bits are asserted in PLB master burst read operations.
To comply with the PCI specification, PLB masters are required to re-issue commands when a PCI retry
is asserted. PCI retries are communicated to the PLB master by asserting PLB rearbitrate without an
interrupt.
It is the responsibility of the master to properly read data from non-prefetchable PCI targets. For
example, the master must perform single transaction reads of non-prefetchable PCI targets to avoid
destructive read operations of a PCI target.
Abnormal Terminations
In the context of the PLB PCI bridge, cacheline transactions are special cases of a burst. Abnormal
terminations during a cacheline read operation have the same response as a burst read transaction.
• If a parity error occurs during the address phase, the PLB PCI Bridge causes an IPIF timeout for
most cases and always asserts the PLB Master Read SERR interrupt. If the remote PCI target follows
the response recommended by the PCI specification to not claim the transactions, the PLB PCI
Bridge terminates the transaction with a master abort and an IPIF timeout occurs. When an IPIF
timeout occurs, Slv_MErr is asserted by the IPIF. If the target does not follow PCI specification
recommendation and transfers data, then depending on the target decode speed and the PLB/PCI
clock ratio, data may be transferred with PLB Master Read SERR interrupt being asserted.
• If a SERR occurs during a valid data phase on a single transfer, the PLB PCI Bridge causes an IPIF
timeout and asserts the PLB Master Read SERR interrupt. When an IPIF timeout occurs, Slv_MErr
is asserted by the IPIF.