Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 50)

PLB PCI Full Bridge (v1.00a)
50 www.xilinx.com DS508 March 21, 2006
Product Specification
EARL
Y ACCESS
subordinate buses. Device numbers are independent for each PLB PCI bridge instantiated, but bus
numbering must be monotonically increasing for all primary buses and their subordinate buses.
Abnormal Terminations
Responses to abnormal terminations of Configuration Read/Writes follow closely to single
reads/writes by a remote PLB master from/to a remote PCI target. Details of each transaction can be
reviewed in the previous sections; however, some differences exist. Shown in
Table 23 is a table
summary of responses to abnormal terminations during configuration transactions. The differences as
compared to PLB master read/writes to remote targets are shown.
Table 23: Response of PLB Master/v3.0 Initiator Configuration Transactions with abnormal condition on
PCI bus
Abnormal condition Configuration Read Configuration Write
SERR (including address phase
parity error)
Return all ones and set PLB
Master Read SERR
interrupt
PLB Master Write SERR interrupt asserted
PLB PCI Bridge Master abort (no
PCI target response)
All 1s are returned PLB Master Abort Write interrupt asserted
Target disconnect without data
(PCI Retry) Automatically retried until
the transfer completes
Automatically retried a parameterized
number of times. If the last of the PCI write
command retries fail due to a PCI retry, the
PLB Master Burst Write Retry interrupt is
asserted. The PLB master must reissue
command per PCI specification, if last
termination was a retry.
Target disconnect with data Completes Completes
PERR
Data is transferred and PLB
Master Read PERR
interrupt is asserted
Transaction completes and PLB Master Write
PERR interrupt asserted
Latency timer expiration
Latency timer register must be
set to non-zero value for
accessing remote devices. N/A because v3.0 core
waits for one transfer after
timeout occurs when
latency timer is non-zero
N/A because v3.0 core waits for one transfer
after timeout occurs when latency timer is
non-zero
Target Abort
Return all ones and set PLB
Master Read Target Abort
interrupt
Assert PLB Master Write Target Abort
interrupt.
Design Implementation
Design Tools
The PLB PCI Bridge design is implemented using the VHDL. All coding standards and abbreviations
specified in IPSPEC001 Virtex-II Pro Coding Standards and IPSPEC002 Virtex-II Pro Standard
Abbreviations have been adhered to.
Xilinx XST and Synplicity’s Synplify Pro synthesis tools are used for synthesizing the PLB PCI Bridge.
The NGC format from XST and EDIF netlist output from Synplify Pro are then input to the Xilinx
Alliance tool suite for actual device implementation.