Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 47)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 47
Product Specification
EAR
LY
ACCESS
bridge is not used. As with Memory and IO data transactions, byte addressing integrity is maintained
in configuration transfers across the bus.
When host bridge configuration functionality is implemented in the PLB PCI bridge, the v3.0 core in
the PLB PCI bridge must be configured first. The minimum that must be set is the Bus master enable bit
in the command register and the latency timer register. This requirement is because the v3.0 core has
the capability to configure only itself until the Bus master enable bit is set in the command register of
the v3.0 core and the latency timer register is properly set to avoid timeouts. If the v3.0 core latency
timer is set to 0 value, configuration writes to remote PCI devices will not complete and configuration
reads of remote PCI devices will terminate due to the latency timer expiration. Configuration reads of
remote PCI devices with the latency timer set to 0 will return 0xFFFFFFFF.
Table 21 shows the results of configuring the v3.0 core configuration header in the PLB PCI bridge by
both PLB-side configuration transactions and by remote PCI host bridge configuration transactions
from the PCI-side. This example assumes all PCI BARs are designated memory space which is the only
allowed PCIBAR memory type. Note that PLB-side configuration of the v3.0 core enables all
functionality in the Command Status Register and sets the latency timer to maximum count for most
any data value written to the registers. This behavior is an artifact of the v3.0 core behavior.
Configuration Space Header
The LogiCORE v3.0 core used in the PLB PCI bridge can be configured with functionality to address a
wide range of applications.
Fields of the Configuration Space Header are Device ID, Vendor ID, Class Code, Rev ID, Subsystem ID,
Subsystem Vendor ID, Maximum Latency and Minimum Grant. The parameters for these fields are
C_DEVICE_ID, C_VENDOR_ID, C_CLASS_CODE, C_REV_ID, C_SUBSYSTEM_ID,
C_SUBSYSTEM_VENDOR_ID, C_MAX_LAT, C_MIN_GNT, respectively.
Listed below are details on the remaining configuration registers that are fixed in value.
BIST, Line Size and Expansion ROM Base Address are not implemented in the LogiCORE v3.0 design.
Header Type is a fixed byte of all zeros in the LogiCORE v3.0 design.
Cardbus CIS Pointer is set to all zeros for the LogiCORE v3.0 implementation used in the PLB PCI
bridge.
Capabilities Pointer is not enabled for the LogiCORE v3.0 implementation used in the PLB PCI bridge.
Interrupt Pin register is set to 0x01.
BAR3, BAR4 and BAR5 are not supported by the LogiCORE v3.0 Core. For these registers and
unimplemented PCIBARs (determined by C_PCIBAR_NUM), zeros are returned when read. Writes to
the unimplemented configuration space addresses have no effect.
Latency timer, BAR0, BAR1, and BAR2 are required to be set by the host bridge as necessary. The
number of BARs (0-3) is set by the parameter C_PCIBAR_NUM.
The User Configuration Space is enabled for the LogiCORE v3.0 implementation used in the PLB PCI
bridge.