Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 7)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 7
Product Specification
EAR
LY
ACCESS
As in example 1, it is assumed that the parameter C_INCLUDE_BAROFFSET_REG=0, therefore the
C_IPIFBAR2PCIBAR_N parameters define the address translation.
In this example, where C_IPIFBAR_NUM=4, the following assignments for each range are made:
C_IPIFBAR_0=0x12340000
C_IPIF_HIGHADDR_0=0x1234FFFF
C_IPIFBAR2PCIBAR_0=0x5671XXXX (Bits 16-31 are don’t cares)
C_IPIFBAR_1=0xABCDE000
C_IPIF_HIGHADDR_1=0xABCDFFFF
C_IPIFBAR2PCIBAR_1=0xFEDC0xXX (Bits 19-31 are don’t cares)
C_IPIFBAR_2=0xFE000000
C_IPIF_HIGHADDR_2=0xFFFFFFFF
C_IPIFBAR2PCIBAR_2=0x40xXXXXX (Bits 7-31 are don’t cares)
C_IPIFBAR_3=0x00000000
C_IPIF_HIGHADDR_3=0x0000007F
C_IPIFBAR2PCIBAR_3=8765438X (Bits 25-31 are don’t cares)
Accessing the PLB PCI Bridge IPIFBAR_0 with address 0x12340ABC on the PLB bus yields
0x56710ABC
on the PCI bus.
Accessing the PLB PCI Bridge IPIFBAR_1 with address 0xABCDF123 on the PLB bus yields
0xFEDC1123
on the PCI bus.
Accessing the PLB PCI Bridge IPIFBAR_2 with address 0xFFFEDCBA on the PLB bus yields
0x41FEDCBA
on the PCI bus.
Accessing the PLB PCI Bridge IPIFBAR_3 with address 0x00000071 on the PLB bus yields
Ox876543F1
on the PCI bus.
Example 3
Example 3 outlines address translation of PCI addresses within the range of a given PCIBAR to PLB
address space. Note that this translation is independent of the PLB PCI Bridge IPIF BARs.
The parameters C_PCIBAR2IPIFBAR_M parameters define the address translation for all
C_PCIBAR_NUM.
In this example, where C_PCIBAR_NUM=2, the following range assignments are made:
BAR 0 is set to 0xABCDE800 by host
C_PCIBAR_LEN_0=11
C_PCIBAR2IPIFBAR_0=0x123450XX (Bits 21-31 are don’t cares)
BAR 1 is set to 0x12000000 by host
C_PCIBAR_LEN_1=25
C_PCIBAR2IPIFBAR_1=0xFEXXXXXX (Bits 7-31 are don’t cares)
Accessing the PLB PCI Bridge PCIBAR_0 with address 0xABCDEFF4 on the PCI bus yields
0x123457F4
on the PLB bus.