Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 37)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 37
Product Specification
EAR
LY
ACCESS
Table 17 summarizes the abnormal conditions with which a PCI target can respond and how the
response is translated to the PLB master.
Table 17: Response of PLB Master/v3.0 Initiator read of a remote PCI target with abnormal condition on
PCI bus
Abnormal condition Single transfer
Burst
(PLB_rdBurst asserted)
SERR (includes parity error on
address phase)
IPIF timeout and Slv_MErr is
asserted (most cases; see above
text) and IPIF Master Read SERR
interrupt asserted IPIF timeout and Slv_MErr is
asserted (most cases; see above
text) and PLB Master Read SERR
interrupt asserted
PLB PCI Bridge Master abort
(no PCI target response) PLB IPIF timeout and Slv_MErr is
asserted PLB IPIF timeout and Slv_MErr is
asserted
Target disconnect without data
(PCI Retry)
Immediate automatic retry Immediate automatic retry
Target disconnect without data
(after one completed data
phase)
N/A
Data is being buffered in PLB PCI
Bridge PCI2IPIF FIFO. The PCI
transaction is terminated by the
disconnect. At a parameterized FIFO
occupancy level, the PLB PCI Bridge
issues another PCI transaction at
correct address. If a PCI retry is
asserted, the PCI read automatically
retried. The bridge inhibits IPIF
timeout while trying to get the
requested data.
Target disconnect with data Completes
PERR
Data is transferred and the PLB
Master Read PERR interrupt
asserted
Data transfer to IPIF is stopped, an
IPIF timeout is allowed which results
in Slv_Err asserted and PLB Master
Read PERR interrupt is asserted
Latency timer expiration
N/A because v3.0 core waits for one
transfer after timeout occurs Same as target disconnect
with/without data
Target Abort
Immediately allow PLB IPIF timeout
which results in Slv_MErr being
asserted and set the PLB Target
Abort Master Read interrupt
Data transfer to IPIF is stopped,
immediately allow PLB IPIF timeout
which results in Slv_MErr being
asserted and assert the PLB Target
Abort Master Read interrupt
Address increments beyond
valid range
N/A
Stop PCI transaction after last valid
address; allow data transfer to IPIF to
continue. IPIF timeout and assertion
of Slv_MErr occurs if the PLB master
request continues when FIFO is
empty.
PLB Master Initiates a Write Request to a PCI Target
This section discusses the operation of an PLB master initiating single, burst and cache line write
transactions to a remote PCI target. All PLB write transactions are posted-writes. Because both single
PLB writes and burst PLB writes to the bridge are fire-and-forget, any error in completing the write
occurs mostly likely after the PLB transaction is completed. The errors are signaled by an interrupt