Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 8)

PLB PCI Full Bridge (v1.00a)
8 www.xilinx.com DS508 March 21, 2006
Product Specification
EARL
Y ACCESS
Accessing the PLB PCI Bridge PCIBAR_1 with address 0x1235FEDC on the PCI bus yields
0xFE35FEDC
on the PLB bus.
Table 1: PLB PCI Bridge Interface Design Parameters
Generic
Feature /
Description
Parameter
Name
Allowable Values
Default
Value
VHDL
Type
Bridge Features Parameter Group
G1 Number of IPIF devices
C_IPIFBAR
_NUM
1-6; Parameters listed
below corresponding to
unused BARs are
ignored, but must be
valid values. BAR label
0 is the required bar for
all values 1-6 and the
index increments from 0
as BARs are added
6 integer
G2 IPIF device 0 BAR C_IPIFBAR_0 Valid PLB address (1)
0xFFFFFFFF
std_logic_
vector
G3
IPIF BAR high address
0 C_IPIFBAR_
HIGHADDR_0
Valid PLB address (1) 0x00000000
std_logic_
vector
G4
PCI BAR to which IPIF
BAR 0 is mapped
unless
C_INCLUDE_BAROFF
SET_REG = 1
C_IPIFBAR2
PCIBAR_0 1
Vector of length
C_PLB_AWIDTH
0xFFFFFFFF
std_logic_
vector
G5
IPIF BAR 0 memory
designator C_IPIF_SPACE
TYPE_0
0 = I/O space
1 = Memory space
1 integer
G6 IPIF device 1 BAR C_IPIFBAR_1 Valid PLB address (1)
0xFFFFFFFF
std_logic_
vector
G7
IPIF BAR high address
1 C_IPIFBAR_
HIGHADDR_1
Valid PLB address (1)
0x00000000
std_logic_
vector
G8
PCI BAR to which IPIF
BAR 1 is mapped
unless
C_INCLUDE_BAROFF
SET_REG = 1
C_IPIFBAR2
PCIBAR_1
Vector of length
C_PLB_AWIDTH
0xFFFFFFFF
std_logic_
vector
G9
IPIF BAR 1 memory
designator C_IPIF_SPACE
TYPE_1
0 = I/O space
1 = Memory space
1 integer
G10 IPIF device 2 BAR C_IPIFBAR_2 Valid PLB address (1) 0xFFFFFFFF
std_logic_
vector
G11
IPIF BAR high address
2 C_IPIFBAR_
HIGHADDR_2
Valid PLB address (1)
0x00000000
std_logic_
vector
G12
PCI BAR to which IPIF
BAR 2 is mapped
unless
C_INCLUDE_BAROFF
SET_
REG = 1
C_IPIFBAR2
PCIBAR_2
Vector of length
C_PLB_AWIDTH
0xFFFFFFFF
std_logic_
vector