Rainbow Electronics AT89C5122 - Manual (Page 118)

118
AT8xC5122/23
4202E–SCR–06/06
Reset Value = 0000 0000b
Table 65. USB Global Interrupt Register - USBINT (S:BDh)
7 6 5 4 3 2 1 0
- - WUPCPU EORINT SOFINT - - SPINT
Bit Number
Bit
Mnemonic Description
7 - 6 -
Reserved
The value read from these bits is always 0. Do not change these bits.
5 WUPCPU
Wake-up CPU Interrupt
This bit is set by hardware when the USB controller is in SUSPEND state and is
re-activated by a non-idle signal FROM USB line (not by an upstream resume).
This triggers a USB interrupt when EWUPCPU is set in the Table on page 119.
When receiving this interrupt, user has to enable all USB clock inputs.
This bit should be cleared by software (USB clocks must be enabled before).
4 EEORINT
End of Reset Interrupt
This bit is set by hardware when a End of Reset has been detected by the USB
controller. This triggers a USB interrupt when EEORINT is set in the Table on
page 119.
This bit should be cleared by software.
3 SOFINT
Start Of Frame Interrupt
This bit is set by hardware when an USB Start Of Frame PID (SOF) has been
detected. This triggers a USB interrupt when ESOFINT is set in the Table on
page 119.
This bit should be cleared by software.
2-1 -
Reserved
The value read from these bits is always 0. Do not change these bits.
0 SPINT
Suspend Interrupt
This bit is set by hardware when a USB Suspend (Idle bus for three frame
periods: a J state for 3 ms) is detected. This triggers a USB interrupt when
ESPINT is set in USBIEN register (Table 66 on page 119).
This bit must be cleared by software before powering the microcontroller down
as it disables the USB pads to reduce the power consumption.