Rainbow Electronics AT89C5122 - Manual (Page 21)

21
AT8xC5122/23
4202E–SCR–06/06
Data Memory
Managament All device versions implements :
- 256 Bytes of RAM to increase data parameter handling and high level language usage
- 512 bytes of XRAM (Extended RAM) to store program data.
RAM Achitecture The internal RAM is mapped into three separate segments :
• The Lower 128 bytes (addresses 00h to 7Fh) are directly and indirectly
addressable.
• The Upper 128 bytes (addresses 80h to FFh) are indirectly addressable only.
• The Special Function Registers (SFRs) (addresses 80h to FFh) are directly
addressable only.
The Upper 128 bytes and SFR’s have the same address space but are physically
separated.
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is in the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
• Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings. If M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
XRAM Achitecture Depending on the state of EXTRAM bit in AUXR register (See Table 5 on page 24), the
MCU fetches data from internal or external XRAM.
If EXTRAM=0 (reset condition), the MCU fetches the data from internal XRAM. The size
of internal XRAM is configured by the bit XRS0 in AUXR register (See Table 5 on page
24).
The XRAM logically occupies the first bytes of external data memory. The bit XRS0 can
be used to hide a part of the available XRAM . This can be useful if external peripherals
are mapped at addresses already used by the internal XRAM.
The XRAM is indirectly addressed, using the MOVX instruction in combination with any
of the registers R0, R1 of the selected bank or DPTR.
For example, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at
address 0A0H rather than external memory.
Table 4. XRAM Size Configuration
XRS0 XRAM size
Address
Start End
0
256 Bytes
(Reset condition)
000h 0FFh
1 512 bytes 000h 1FFh