Rainbow Electronics AT89C5122 - Manual (Page 44)

44
AT8xC5122/23
4202E–SCR–06/06
Figure 20. Clock Tree Diagram
CPU and Peripheral Clocks Two clocks sources are available for CPU and peripherals:
– on-chip oscillator
– a derivative of the PLL clock.
These clock sources are configured by the PR1 prescaler to generate the CPU core
CK_CPU and the peripheral clocks:
– CK_IDLE for alternate card and peripherals registers access
– CK_T0 for Timer 0
– CK_T1 for Timer 1
– CK_SI for the UART
– CK_WD for the Watchdog Timer
– CK_SPI for SPI
Alternate
Card
XTAL1
XTAL2
PD
PCON.1
96 MHz
EXT48
PLLCON.2
0
1
0
1
CKS
CKSEL.0
0
1
X2
CKCON0.0
PR1
CKRL[3:0]
IDL
PCON.0
DC/DC
PR4
PR2
CK_IDLE
PR3
Converter
1/2
CK_USB
0
1
CK_ISO
CK_CPU
CK_XTAL1
CK_PLL
DCCKPS[3:0]
SCICLK[5:0]
SCSR[3:2]
1
0
PeriphX2
CKCON0.X or
1
0
X2
CKCON0.0
CK_T0
Peripherals
CK_T1
CK_SI
CK_WD
CK_SPI
CK_PERIPH
CK_IDLE
CK_IDLE
PLLEN
PLLCON.1
CK_XTAL1
CK_PLL
CK_PLL
CK_XTAL1
CK_XTAL1
PERIPH = T0, T1, SI, WD or SPI
CKCON1.0
XTSCS
SCICLK.7
CPU
SCIB
USB
PLL
CK_DCDC
1/2
SCICLK[5:0]
=48
<48