Rainbow Electronics AT89C5122 - Manual (Page 177)

177
AT8xC5122/23
4202E–SCR–06/06
Watchdog Timer The AT8xC5122/23 microcontrollers contain a powerfull programmable hardware
Watchdog Timer (WDT) that automatically resets the chip if its software fails to reset the
WDT before the selected time interval has elapsed. It permits large timeout ranking from
4ms to 524ms @
F
CK_WD
= 24 MHz / X2
This WDT consist of a 14-bit counter plus a 7-bit programmable counter, a Watchdog
Timer reset register (WDTRST) and a Watchdog Timer programmation (WDTPRG) reg-
ister. When exiting the reset, the WDT is, by default, disabled. To activate the WDT, the
user has to write the sequence 1EH and E1H into WDRST register. When the Watchdog
Timer is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or
WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at
the RST pin. The RESET pulse duration is 96xT
OSC
, where T
OSC
=1/F
OSC
. To make the
best use of the WDT, it should be serviced in those sections of code that will periodically
be executed within the time required to prevent a WDT reset.
The WDT is controlled by two registers (WDTRST and WDTPRG).
Figure 108. Watchdog Timer
RESET
Decoder
Control
WDTRST
WR
Enable
14-bit COUNTER 7 - bit COUNTER
Outputs
F
CK_WD
RESET
- - - - - 2 1 0
WDTPRG